`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:59:30 08/29/2012
// Design Name:   pru_fms_timer
// Module Name:   C:/Users/maye/Desktop/alle archivos/lab2/pru_pru_fms_timer.v
// Project Name:  lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: pru_fms_timer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module pru_pru_fms_timer;

	// Inputs
	reg [3:0] value;
	reg clk_i;
	reg clk_largo;
	reg reset;
	reg reset_sync;
	reg sensor_sunc;
	reg prog_sync;

	// Outputs
	wire [7:0] busleds;
	wire [1:0] interval;
	wire wr_reset;

	// Instantiate the Unit Under Test (UUT)
	pru_fms_timer uut (
		.value(value), 
		.clk_i(clk_i),
		.clk_largo(clk_largo),		
		.reset(reset), 
		.reset_sync(reset_sync), 
		.sensor_sunc(sensor_sunc), 
		.prog_sync(prog_sync), 
		.busleds(busleds), 
		.interval(interval), 
		.wr_reset(wr_reset)
	);
	
	always begin #50 clk_largo=~clk_largo;end
	always begin #20 clk_i=~clk_i;end
	
	initial begin
		// Initialize Inputs
		value = 6;
		clk_i = 0;
		clk_largo = 0;
		reset = 0;
		reset_sync = 0;
		sensor_sunc = 0;
		prog_sync = 0;

		// Wait 100 ns for g lobal reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

